MM-1200 VPX Intelligent IO Carrier for XMC/PMCs with x4 sRapidIO ports


  • 2x CoSine 2VP100 System-on-Chips
  • 2x PMC/XMC sites
  • 6 Independent memory arrays with total bandwidth of over 6GBps
  • 4x Embedded PowerPCTM processors
  • Complete Serial RapidIO x4 connectivity
  • 6U VPX (VITA-46) form factor
  • Rugged air-cooled and conduction-cooled variants

The MM-1200 is a VPX (VITA 46) board which enables direct interfacing from a Serial RapidIO (sRIO) based fabric to onboard devices like PMC and XMC sites, large amounts of SDRAM and the CoSine System-on-Chips.

The MM-1200 contains dual CoSine™ System-on-Chips. Each CoSine device is embedded in a Xilinx® Virtex™-II Pro FPGA. Each CoSine device contains two embedded PowerPC™ 405GP devices. The PowerPC processors enable the MM-1200 to be used as a XMC/PMC carrier and memory buffer, as well as a VITA 46 (VPX) based standalone single board computer. In addition to making  the PowerPC 405GP processors accessible, each CoSine node also has one multi-ported DDR array, a dedicated 128MB DDR array to each PowerPC processor and FPGA platform FLASH. The CoSine nodes interface with the two mezzanine sites on the MM-1200 by either an XMC or PMC interface.

Mezzanine Sites
The MM-1200 can support either PMCs or XMCs. Using the PMC sites, each PCI bus can operate in 32-bit or 64-bit PCI 2.3 mode at up to 66MHz or in 64-bit PCI-X mode at up to 133MHz. Using the XMC sites, the MM-1200 supports the Aurora™ protocol with four MGTs or Serial RapidIO x4.

Backplane Connectivity
In addition to having a VME320 2eSST interface, the MM-1200 includes a complete on-board Serial RapidIO switch fabric connectivity, with four independent Serial RapidIO ports to the VITA 46 P1 MGT backplane connector per the VITA 46.3 draft standard.

CoSine Systems-on-Chip
The MM-1200 contains two independent CoSine SoCs. A single SoC is comprised of a CoSine Device (Virtex-II Pro 2VP100) and

  • Two embedded PowerPC 405GP processors
  • One multi-ported primary DDR array, up to 1GB, for seamless bus translation between the mezzanine port and crossbar port to the backplane
  • Two dedicated 128MB DDR arrays local to each PowerPC processor
  • FPGA Platform FLASH

Aggregate memory bandwidth exceeds 3GB/s per SoC, providing a total of over 6GB/s on the MM-1200.

PowerPC Processors and Infrastructure

Each of the two embedded PowerPCs in each 2VP100 is a fully functional computer. Each PowerPC contains its own DDR array, programmable FLASH, and UART. The PowerPC processors also share an Ethernet connection. Processors can host device drivers, perform message passing, service interrupts, or execute floating point operations. Each processor includes a complete BSP with all internal SoC device drivers fully integrated so customers can download application files “out of the box”.

Temperature Sensing
The MM-1200 monitors the temperatures of the CoSine devices, and primary circuit board to ensure proper operation. Status updates can be received by the CoSine PowerPC processors that can then make intelligent decisions, display status to user programmable LEDs, or communicate information over its Ethernet link to remote destinations.

Debug Ports

Debug ports include four RS-232 UART consoles, one board/system push button reset switch, and two processor JTAG debug ports. Debug ports are available out the front panel or backplane via P0.

Ruggedized Options

The MM-1200DR is a rugged, extended temperature air-cooled board with an operating temperature of -40°C to +71°C. The MM-1200DTE is a rugged, conduction-cooled board with an operating temperature of -40°C to +85°C. Both the MM-1200DR and MM-1200DTE have been designed for optimal heat dissipation and deployment in environments that undergo severe shock and vibration.

* Note: while the MM-1200 is designed to meet these environmental requirements, formal qualification testing has not been performed to these levels. Please contact your local sales representative to discuss your program specific requirements.

Last updated: Apr 07 2008, 05:24PM